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Backend Master DMA Register Access Signals
Backend Master DMA Register Access Signals
The signals listed in Table 5-6 are used to allow the backend to access the internal Target configuration space and DMA
registers to initiate DMA Master transfers. These signals only function when the BACKEND parameter is set. The
interface supports byte-wide operations if required. All these inputs and outputs are synchronous to the PCI clock.
Table 5-6 · Backend DMA Register Access Signals
Name
BE_REQ
Type
Input
Width
1
Description
A request from the backend to the core to take control of the backend interface. This signal is
active high, and should be synchronous to the PCI clock.
A grant from the core giving control to the backend logic.
When the BE_GNT signal is active and a transaction to the PCI Target controller occurs, the
BE_GNT
Output
1
PCI controller will respond with a retry cycle. If a PCI cycle is in progress when BE_REQ is
asserted, BE_GNT will not assert until completion of the current PCI cycle.
If the backend must take control during an active PCI transfer cycle, it may assert the STOP or
STOP_MASTER inputs, causing the current PCI cycle to terminate.
Active high synchronous read enable for the DMA registers. It will be ignored if BE_GNT is
BE_READ
Input
1
inactive. During read cycles, there is a two-clock-cycle latency from BE_READ and
BE_ADDRESS to valid data on MEM_DATA_OUT.
Active high synchronous write enable for the DMA registers. One enable is provided for each of
BE_WRITE
Input
4
the four bytes; BE_WRITE[0] active will write bits [7:0] and will be ignored if BE_GNT is
inactive.
BE_ADDRESS
Input
8
Address input that addresses the 256-byte configuration space. The lower two bits are ignored.
The DMA registers are at addresses 50, 54, 58, and 5C hex.
When 0, the complete internal configuration space can be read from and written to the backend
interface.
BE_CFGLOCK
Input
1
When 1, the main PCI configuration space (00–3F hex) can only be read; writes are prevented.
This prevents the backend interface from modifying the PCI configuration space and potentially
causing errors on the PCI bus. Writes to the DMA control registers are still allowed.
v4.0
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